
#include <xmc4500/io.h>
#include "xmc_gpio.h"


/*
This is the routine that allows us to enable all of the task scheduler timer
interrupts once we have configured the task scheduler
*/

void enable_task_timers(void)
{
    NVIC_EnableIRQ(CCU43_0_IRQn);
    NVIC_EnableIRQ(CCU43_1_IRQn);
    NVIC_EnableIRQ(CCU43_2_IRQn);
    //NVIC_EnableIRQ(VADC0_G1_3_IRQn); //disable  this slice
}



/*
This is the adc interrupt enable, that is called once
the motor controller is ready
*/

void enable_sys_tick_interrupt(void)
{
    /* Set up SysTick at 100uS = 10kHz*/
    SysTick_Config(120000000L/10000);
    NVIC_SetPriority(SysTick_IRQn, 4);
}


/*=============================================================================
 * *IO_vInit :: Initialize the io Port System
 *===========================================================
 *
 */
void IO_vInit(void)
{
    XMC_GPIO_CONFIG_t stGPIOConfig;

    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P1_8, &stGPIOConfig);

    /*digital output*/

    /*FAN_CONTROLLER_OUT_LS_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P0_2, &stGPIOConfig);

    /*INV1_ENABLE_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P0_3, &stGPIOConfig);

    /*tlf cs*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;

    XMC_GPIO_Init(P2_3, &stGPIOConfig);

    /*DCDC_CONTROL_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P0_4, &stGPIOConfig);

    /*BUZZER_OUT_LS_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P0_9, &stGPIOConfig);
    
    /*FAN_MOTOR_OUT_LS_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P0_10, &stGPIOConfig);

    /*I2C_WP_CPU_M*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;

    XMC_GPIO_Init(P0_12, &stGPIOConfig);
    

    /*DC_LINK_PRECHAGE_EN_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P1_6, &stGPIOConfig);

    /*RESERVE_2_IN_ON_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P1_7, &stGPIOConfig);


    /*INV2_ENABLE_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P1_9, &stGPIOConfig);

    /*TLF_MPS_CON*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /*to disable tlf monitor function*/

    XMC_GPIO_Init(P2_14, &stGPIOConfig);

    /*ALARM_BUZZER_OUT_LS_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; /*to disable tlf monitor function*/

    XMC_GPIO_Init(P2_15, &stGPIOConfig);
    

    /*LED_0805_GE*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P3_6, &stGPIOConfig);

    /*RESET_ERROR_CPU_V*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;

    XMC_GPIO_Init(P5_7, &stGPIOConfig);

    /*EN_TLF_ERR*/
    stGPIOConfig.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
    stGPIOConfig.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
    XMC_GPIO_Init(P3_5, &stGPIOConfig);

    /*digital input*/
    
    /*FORWARD_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P0_1, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*/BOOT_ANCHOR_CPU_M*/ 
    XMC_GPIO_SetMode(P1_0, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*SEAT_SWITCH_NC_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_1, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*NEUTRAL_POSITION_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_8, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*REVERSE_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_10, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*LIFT_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_11, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*TILT_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_12, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*MAST_AUX_1_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_13, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*MAST_AUX_2_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_14, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*SEAT_SWITCH_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P1_15, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*RESERVE_1_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P2_0, XMC_GPIO_MODE_INPUT_TRISTATE); 

    /*MAIN_CONTACTOR_ERROR*/ 
    XMC_GPIO_SetMode(P2_8, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CUT-OFF_ISO_VALVE_ERROR*/ 
    XMC_GPIO_SetMode(P2_9, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*BUZZER_ERROR*/ 
    XMC_GPIO_SetMode(P2_10, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CPU_SYNC*/ 
    XMC_GPIO_SetMode(P3_1, XMC_GPIO_MODE_INPUT_TRISTATE); 
    
    /*TLF_INT*/ 
    XMC_GPIO_SetMode(P3_2, XMC_GPIO_MODE_INPUT_TRISTATE); 

    /*PARK_BRAKE_IN_D_CPU_V*/ 
    XMC_GPIO_SetMode(P3_3, XMC_GPIO_MODE_INPUT_TRISTATE); 

    /*EN_TLF_SAFESTATE1*/ 
    XMC_GPIO_SetMode(P3_4, XMC_GPIO_MODE_INPUT_TRISTATE); 

    /*FAN_ERROR*/ 
    XMC_GPIO_SetMode(P5_2, XMC_GPIO_MODE_INPUT_TRISTATE);


    /*CURRENT_INV1_U_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_0, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*TEMP_MOT_INV2_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_1, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*+5V_EXTERNAL_SENSORS_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_2, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CURRENT_INV1_W_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_3, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CURRENT_INV2_U_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_4, XMC_GPIO_MODE_INPUT_TRISTATE);
    
    /*DC_LINK_+_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_5, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*ACCELERATOR_1_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_6, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*+13.7V_SUPPLY_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_7, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*STEER_ANGLE_B_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_8, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*RESERVE_2_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_9, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*TEMP_MOT_INV1_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_12, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CURRENT_CUT-OFF_ISO_VALVE_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_13, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*ACCELERATOR_2_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_14, XMC_GPIO_MODE_INPUT_TRISTATE);
    
    /*CURRENT_MAIN_CONTACTOR_A_CPU_V*/ 
    XMC_GPIO_SetMode(P14_15, XMC_GPIO_MODE_INPUT_TRISTATE);
    

    /*RESERVE_1_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P15_2, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*STEER_ANGLE_A_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P15_3, XMC_GPIO_MODE_INPUT_TRISTATE);

    /*CURRENT_INV2_W_A_CPU_V*/ 
    XMC_GPIO_SetMode(P15_8, XMC_GPIO_MODE_INPUT_TRISTATE);
    
    /*KEY_SWITCH_IN_A_CPU_V*/ 
    XMC_GPIO_SetMode(P15_9, XMC_GPIO_MODE_INPUT_TRISTATE);


    /* Disable clock gating */

    /* Bring modules out of reset*/

    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_VADCRS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_USIC0RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_CCU80RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_CCU81RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_CCU40RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_CCU41RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_CCU42RS_Pos);
    SET_BIT(SCU_RESET->PRSET0, SCU_RESET_PRCLR0_POSIF0RS_Pos);

    SET_BIT(SCU_RESET->PRSET1, SCU_RESET_PRCLR1_CCU43RS_Pos);
    SET_BIT(SCU_RESET->PRSET1, SCU_RESET_PRCLR1_USIC1RS_Pos);
    SET_BIT(SCU_RESET->PRSET1, SCU_RESET_PRCLR1_MCAN0RS_Pos);

    SET_BIT(SCU_RESET->PRSET2, SCU_RESET_PRCLR2_DMA0RS_Pos);
    

    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_VADCRS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_USIC0RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_CCU80RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_CCU81RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_CCU40RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_CCU41RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_CCU42RS_Pos);
    SET_BIT(SCU_RESET->PRCLR0, SCU_RESET_PRCLR0_POSIF0RS_Pos);

    SET_BIT(SCU_RESET->PRCLR1, SCU_RESET_PRCLR1_CCU43RS_Pos);
    SET_BIT(SCU_RESET->PRCLR1, SCU_RESET_PRCLR1_USIC1RS_Pos);
    SET_BIT(SCU_RESET->PRCLR1, SCU_RESET_PRCLR1_MCAN0RS_Pos);

    SET_BIT(SCU_RESET->PRCLR2, SCU_RESET_PRCLR2_DMA0RS_Pos);

    SCU_CLK->CLKSET |= (uint32_t)SCU_CLK_CLKSET_CCUCEN_Msk;

    // 1mS Interrupt*/

    SCU_GENERAL->CCUCON |=(1 << SCU_GENERAL_CCUCON_GSC43_Pos); /*CCU43_CC42 global enable*/
    CCU43->GIDLC |= (1 << CCU4_GIDLC_CS0I_Pos);                /*CC43 Idle clear*/
    CCU43->GIDLC |=(1 << CCU4_GIDLC_SPRB_Pos);                 /*Prescaller Run Bit set*/
    CCU43_CC40->PSC = 1;                                       /*Prescaller select->2^1*/
    CCU43_CC40->INTE = 0x401;                                  /*Timer Run Bit set*/
    CCU43_CC40->SRS = 0;                                       /*Source = 0*/
    CCU43_CC40->PRS = 0xea5f;                                  /*Period set = 120e6 Hz / (2 * 1kHz) - 1*/
    CCU43_CC40->CRS = CCU43_CC40->PRS >> 1;                    /*Duty Sycle set*/
    CCU43->GCSS |= (1 << CCU4_GCSS_S0SE_Pos);                  /*Shadow transfer request*/
    CCU43_CC40->TCSET = 1;                                     /*Timer Run Bit set*/

    // 10mS Interrupt*/

    CCU43->GIDLC |= (1 << CCU4_GIDLC_CS1I_Pos);                /*CC43 Idle clear*/
    CCU43->GIDLC |=(1 << CCU4_GIDLC_SPRB_Pos);                 /*Prescaller Run Bit set*/
    CCU43_CC41->PSC = 5;                                       /*Prescaller select->2^5*/
    CCU43_CC41->INTE = 0x401;                                  /*Enable interrupt*/
    CCU43_CC41->SRS = 1;                                       /*Source = 1*/
    CCU43_CC41->PRS = 0x927B;                                  /*Period set = 120e6 Hz / (32 * 100Hz) - 1*/
    CCU43_CC41->CRS = CCU43_CC40->PRS >> 1;                    /*Duty Sycle set*/
    CCU43->GCSS |= (1 << CCU4_GCSS_S1SE_Pos);                  /*Shadow transfer request*/
    CCU43_CC41->TCSET = 1;                                     /*Timer Run Bit set*/

    // 100mS Interrupt*/

    CCU43->GIDLC |= (1 << CCU4_GIDLC_CS2I_Pos);                /*CC43 Idle clear*/
    CCU43->GIDLC |=(1 << CCU4_GIDLC_SPRB_Pos);                 /*Prescaller Run Bit set*/
    CCU43_CC42->PSC = 8;                                       /*Prescaller select->2^8*/
    CCU43_CC42->INTE = 0x401;                                  /*Enable interrupt*/
    CCU43_CC42->SRS = 2;                                       /*Source = 2*/
    CCU43_CC42->PRS = 0xB71A;                                  /*Period set = 120e6 Hz / (256 * 10Hz) - 1*/
    CCU43_CC42->CRS = CCU43_CC42->PRS >> 1;                    /*Duty Sycle set*/
    CCU43->GCSS |= (1 << CCU4_GCSS_S2SE_Pos);                  /*Shadow transfer request*/
    CCU43_CC42->TCSET = 1;                                     /*Timer Run Bit set*/

    CLR_BIT(SCU_GENERAL->DTSCON, SCU_GENERAL_DTSCON_PWD_Pos);
    SET_BIT(SCU_GENERAL->DTSCON, SCU_GENERAL_DTSCON_START_Pos);

    /* Configure Interrupts*/
    NVIC_SetPriorityGrouping(0);

    NVIC_SetPriority(CCU43_0_IRQn,    CCU43_0_INT_PRI);          /* 1mS Interrupt*/
    NVIC_SetPriority(CCU43_1_IRQn,    CCU43_1_INT_PRI);          /* 4mS Interrupt*/
    NVIC_SetPriority(CCU43_2_IRQn,    CCU43_2_INT_PRI);          /* 10mS Interrupt*/
}



